Fault Injection and Test Flow for MIPS

This flow mimics the effect of hardware faults on a MIPS processor. For a given program, it produces a list of the instruction types that are affected by gate-level faults. If the hardware has no faults, the list is empty; its contents vary from program to program. It was developed for the URISC project (see Research). The package is available on request; please contact us.

Test structure

Faulty MIPS test structure

Figure 1. Faulty MIPS test structure.

Two MIPS processors run the same program on the same clock: one is fault-free, and the other has injected gate-level faults. During simulation, the outputs of the decode stages (or the execute stages, depending on where the faults are) are compared. When they differ, the instruction is recorded as affected, and the list is extracted when the program finishes. For clarity, the schematics do not show every interconnection.

The flow has four parts:

  1. Generate the gate-level netlist for the modules that will receive faults.
  2. Introduce faults into that netlist.
  3. Simulate the faulty MIPS.
  4. Collect and analyze the data.

Part 1: Generate the gate-level netlist

Faults are injected into simple gates, so you need a pure gate-level netlist for each module of interest (in our case the branch unit, decoder, ALU and shifter). First create a BLIF netlist with Quartus II, then convert it to an AIG (and-inverter graph) netlist in Verilog with ABC.

Phase 1: Create a BLIF netlist with Quartus II. Install Quartus II and Altera’s Quartus II University Interface Program (QUIP), which lets Quartus II write a technology-independent BLIF netlist for a module. Then:

  1. Create a new Quartus II project for the module.
  2. Add this line to the project’s settings file (.qsf): 
    set_global_assignment -name INI_VARS "no_add_ops=on;opt_dont_use_mac=on;dump_blif_before_optimize=on"
  3. Synthesize the module. The BLIF netlist is written to the folder that holds the .qsf file.

Phase 2: Convert the BLIF netlist to an AIG with ABC. The BLIF netlist from QUIP is not yet gate-level, so use ABC to convert it to an AIG and write it out as Verilog:

  1. Read the netlist, building an AIG: read_blif -a your_module_netlist.blif
  2. Write it as Verilog: write_verilog your_module.v

Part 2: Introduce faults in the netlist

Run the Python script add_fault_exhaustive.py in the 4Python folder. It injects faults node by node, either exhaustively or in order, and writes one faulty netlist per faulty node. Before running it, rename the AIG Verilog netlist from Part 1 (for example tiger_decoder_blif.v) to netlist.txt and place it next to the script. See the readme in 4Python/add_fault_exhaustive for details.

Part 3: Simulate the faulty MIPS

Set up the ModelSim simulation in the 1Modelsim folder. altera_lib is the library used by Tiger MIPS (from the LegUp group at the University of Toronto); readme_dan.txt in 1Modelsim explains the other folders. You also need a .dat file for your program, placed where both the fault-free and faulty processors can read it; readme_dan.txt in 6Windows_Tools explains how to create it.

Part 4: Collect and analyze the data

Extract the affected instructions from the ModelSim transcript files, either with your own script or with multi_trans_extract.py. See the readme in 4Python/multi_trans_extract for details.

Example

MIPS five-stage pipeline and an example test flow

Figure 2. The five-stage MIPS pipeline and an example test flow.

In this example, the ALU in the execute stage is faulty. Going through the four parts above produces the list of instructions affected by that fault.

If you get stuck, check the readme_dan.txt file in each sub-folder.

The flow was developed by Dan Wang in 2013.

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