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2022
2022
Predictable Sharing of Last-level Cache Partitions for Multi-core Safety-critical Systems.
In proceedings of IEEE Design Automation Conference (DAC), pp. 1–6, 2022.
2021
A Hardware Platform for Exploring Predictable Cache Coherence Protocols for Real-time Multicores
.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, 2021.
A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, 2021.
Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols.
In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1–6, 2021.
A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms.
In proceedings of IEEE Design Automation Conference (DAC), pp. 685–690, 2021.
Task Mapping and Scheduling for OpenVX Applications on Heterogeneous Multi/Many-core Architectures.
In IEEE Transactions on Computers (TC), pp. 1–14, 2021.
2020
Gretch: A Hardware Prefetcher for Graph Analytics.
In ACM Transactions on Architecture and Code Optimization (TACO), pp. 1–25, Nov. 2020.
Designing Predictable Cache Coherence for Multi-core Real-Time Systems.
In IEEE Transactions on Computers (TC), pp. 1–16, Nov. 2020.
On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications
on Heterogeneous Multi/Many-core Architectures.
In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1003–1006, 2020.
2019
Technical Report: PENDULUM: A Cache Coherence Protocol for Mixed Criticality Systems.
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems.
In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, 2019.
CARP: A Data Communication Mechanism for Multi-Core Mixed-Criticality Systems.
In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, 2019.
Strengthening PUFs using Composition.
In proceedings of IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–8, 2019.
Strengthening PUFs using Composition.
In IEEE Transactions on Computers, pp. 1–14, 2019.
Languages, Design Methods, and Tools for Electronic System Design
- Selected Contributions from FDL 2017 [Verona, Italy, September
18-20, 2017].
Springer, 2019
2018
A Comparative Study of Predictable DRAM Controllers.
In ACM Transactions on Embedded Computing Systems (TECS), vol. 17, pp. 53:1–53:23, Nov. 2018.
Technical Report for Modeling Attacks on State-of-the-art PUF Architectures.
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 5, pp. 1050–1063, 2018.
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis.
In ACM Transactions on Embedded Computing Systems (TECS), vol. 17, no. 5, pp. 90:1–90:25, 2018.
2017
Technical Report for HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores.
PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality.
In ACM Transactions on Embedded Computing Systems (TECS), vol. 16, pp. 100:1–100:28, May 2017.
Predictable cache coherence for multi-core real time systems.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 235–246, 2017.
HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical
Multi-Core Systems.
In CoRR, vol. abs/1706.07568, 2017.
Applying Models of Computation to OpenCL Pipes for FPGA Computing.
In Proceedings of the 5th International Workshop on OpenCL, New York, NY, USA, pp. 9:1–9:4, 2017.
2016
MCXplore: An Automated Framework for Validating Memory Controller Designs.
In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1357–1362, 2016.
Path Selection for Real-Time Communication on Priority-Aware NoCs.
In ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 53:1–53:25, Jul. 2016.
Buffer Space Allocation for Real-Time Priority-Aware Networks.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 255–266, 2016.
Criticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality Systems.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 73–83, 2016.
2015
Reverse-engineering Embedded Memory Controllers through Latency-based analysis.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 297–306, 2015.
A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 307–316, 2015.
Static slack-based instrumentation of programs.
In 20th IEEE Conference on Emerging Technologies & Factory Automation, ETFA, pp. 1–8, 2015.
SLA: A Stage-level Latency Analysis for Real-time Communication in a Pipelined Resource Model.
In IEEE Transactions on Computers, vol. 64, pp. 1177–1190, Apr. 2015.
2014
Reliable Computing with Ultra-Reduced Instruction Set Co-processors.
In IEEE Micro, vol. 34, no. 6, pp. 86–94, Dec. 2014.
Bounding Buffer Space Requirements for Real-Time Priority-Aware Networks.
In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 113–118, 2014.
On the Semantics of Control-Operation-Integrated Synchronous Dataflow: Schedulability and Parallelism.
In ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1–25, 2014.
2013
An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 11, pp. 1819–1823, Nov. 2013.
systemc-clang: An Open-source Framework for Analyzing Mixed-abstraction SystemC Models.
In proceedings of IEEE Forum on Specification and Design Languages (FDL), pp. 1–8, 2013.
ORTAP: An Offset-based Response Time Analysis for a Pipelined Communication Resource Model.
In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 247–258, 2013.
On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications.
In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1357–1366, 2013.
Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors.
In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 933–938, 2013.
2012
Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors.
In 3^rd Workshop on Resilient Architectures (WRA), In conjunction with IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 1–4, 2012.
Accelerating SystemC Simulations using GPUs.
In proceedings of IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 132–139, 2012.
synASM: A High-level Synthesis Framework that Supports Explicit Parallel and Timed Constructs.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 10, pp. 1508–1521, Oct. 2012.
Accelerating SystemC Simulations using GPUs.
HolisticNoC: A NoC-Aware Holistic Analysis for Distributing Hard Real-time Systems on CMPs.
Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs.
In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 455–460, 2012.
Predictable and Parallel Execution of Real-Time Applications on Cache-Coherent Multicores.
In proceedings of IEEE Euromicro Conference on Real-Time Systems (ECRTS), pp. 1–10, 2012.
Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs.
In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 499–504, 2012.
A Link-level Analysis for Real-time Communication on Network-on-Chips.
In proceedings of IEEE Euromicro Conference on Real-Time Systems (ECRTS), pp. 1–10, 2012.
Reliable Computing with Ultra-Reduced Instruction-Set Co-processors.
In proceedings of IEEE Design Automation Conference (DAC), New York, NY, USA, pp. 697–702, 2012.
lintASM: Static Detection of State Conflicts for Explicitly Parallel and Timing Constructs in High-level Synthesis.
Reliable Computing with Ultra-Reduced Instruction-Set Co-processors.
An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 659–664, 2012.
Robust Optimization for Power-Aware Capacity Planning of Heterogeneous Data Centers.
In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1–6, 2012.
Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs.
Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs.
Time-Aware Instrumentation on the Worst-Case Path.
In Real-Time Systems (RTS), pp. 1–12, 2012.
2011
Robust Heterogeneous Data Center Design: A Principled Approach.
In ACM SIGMETRICS Performance Evaluation Review (PER), vol. 39, no. 3, pp. 28–30, Dec. 2011.
Time-aware Instrumentation of the Worst-case Path.
In proceedings of ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), pp. 1–10, 2011.
A Link-level Analysis for Real-time Communication on Network-on-Chips.
In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–10, 2011.
PRET DRAM Controller: On the Virtue of Privitization.
In proceedings of ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES/ ISSS), pp. 99–108, 2011.
An Authorization Scheme for Version Control Systems.
In proceedings of ACM Symposium on Access Control Models and Technologies (SACMAT), New York, NY, USA, pp. 123–132, 2011.
Temporal Isolation on Multiprocessing Architectures.
In proceedings of IEEE Design Automation Conference (DAC), pp. 274–279, 2011.
Abstract State Machines as an Intermediate Representation for High Level Synthesis.
In proceedings of IEEE Design, Automation and Test in Europe (DATE), pp. 1–6, 2011.
A Case for Instruction Subset Architectures (I_SA) – Guaranteeing Functionality in High Defect Rate Technologies.
In ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Session on Ideas and Perspectives, pp. 1–2, 2011.
Extending Force-directed Scheduling with Explicit Parallel and Timed Constructs for High-level Synthesis.
In proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 214–217, 2011.
Robust Heterogeneous Data Center Design:A Principled Approach.
In proceedings of Workshop on Mathematical Performance Modeling and Analysis (MAMA), pp. 1–4, 2011.
2010
A Hardware/Software Co-design Framework using Abstract State Machines.
In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 53–58, 2010.
Deploying Hard Real-time Control Software on CMPs.
In International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 283–292, 2010.
Towards A Multi-MoC Hardware/Software Co-design Framework using Abstract State Machines.
SCGPSim: A fast SystemC simulator on GPUs.
In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 149–154, 2010.
2009
A Disruptive Computer Design Idea: Architectures with Repeatable Timing.
In proceedings of IEEE International Conference on Computer Design (ICCD), pp. 54–59, 2009.
Generating Multi-threaded code from Polychronous Specifications.
In Electronic Notes in Theoretical Computer Science, vol. 238, no. 1, pp. 57–69, Jun. 2009.
Poster Abstract: Timing Instructions - ISA Extensions for Timing Guarantees.
In proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–2, 2009.
Using a Model Checker to Determine Worst-case Execution Time.
Computer Science Technical ReportReconciling repeatable timing with pipelining and memory hierarchy.
In proceedings of the Workshop on Reconciling Performance with Predictability (RePP), pp. 1–6, 2009.
2008
A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture.
EECS Department, University of California, BerkeleyPredictable Programming on a Precision Timed Architecture.
In proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), pp. 137–146, 2008.
An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture.
In proceedings of the IEEE International Symposium on Distributed Simulation and Real Time Applications (DSRT), pp. 322–325, 2008.
A Scratchpad Memory Allocation Scheme for Dataflow Models.
EECS Department, University of California, BerkeleyIngredients for Successful System Level Design Methodology.
Springer Netherlands, pp. p. 208, , 2008
SML-Sys: A Functional Framework with Multiple Models of Computation for Modeling Heterogeneous System.
In Design Automation for Embedded Systems, vol. 12, no. 1–2, pp. 1–30, Jun. 2008.
On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications.
In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 129–138, 2008.
EWD: A Metamodeling Driven Customizable Multi-MoC System Modeling Environment.
In ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 12, no. 3, pp. 1–43, May 2008.
PTIDES: A Programming Model for Distributed Real-Time Embedded Systems.
EECS Department, University of California, BerkeleyModel-driven Validation of SystemC Designs.
In EURASIP Journal on Embedded Systems, vol. 2008, pp. 1–14, Apr. 2008.
Toward an Effective Execution Policy for Distributed Real-Time Embedded Systems.
In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Work-in-Progress Session, pp. 1–4, 2008.
Exploring Power Management in Multi-core Systems.
In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 708–713, 2008.
On Cosimulating Multiple Abstraction-Level System-Level Models.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 2, pp. 394–398, Feb. 2008.
2007
Model-driven Validation of SystemC Designs.
In proceedings of ACM/IEEE Design Automation Conference (DAC), New York, NY, USA, pp. 29–34, 2007.
Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL.
In proceedings of Design, Automation and Test in Europe Conference (DATE), pp. 279–284, 2007.
Heterogeneous Behavioral Hierarchy Extensions for SystemC.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 4, pp. 765–780, Apr. 2007.
Performance modeling for early analysis of multi-core systems.
In proceedings of IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis (CODES/ISSS), pp. 209–214, 2007.
2006
Deep vs. Shallow, Kernel vs. Language–What is Better for Heterogeneous Modeling in SystemC?
In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 68–75, 2006.
CARH: A Service-oriented Architecture for Validating System-level Designs.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 8, pp. 1458–1474, Aug. 2006.
A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design.
In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 39–48, 2006.
Heterogeneous Behavioral Hierarchy for System Level Designs.
In proceedings of Design, Automation and Test in Europe (DATE), pp. 565–570, 2006.
Design Issues for Networked Embedded Systems.
In Handbook of Information Technology,
R. Zurawski, Ed. CRC Press, 2006, pp. pp. 1–18
2005
Automated Extraction of Structural Information from SystemC-based IP for Validation.
In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 99–104, 2005.
Towards Behavioral Hierarchy Extensions for SystemC.
In proceedings of Forum on Design and Specification Languages (FDL), pp. 361–373, 2005.
Modeling environment for heterogeneous systems based on generic MoCs.
In proceedings of Forum on Design and Specification Languages (FDL), pp. 291–303, 2005.
SystemCXML: An extensible SystemC front end using XML.
In proceedings of Forum on Design and Specification Languages (FDL), pp. 405–409, 2005.
SystemC Kernel Extensions for Heterogeneous System Modeling.
Springer United States, pp. p. 172, , 2005
Towards a Heterogeneous Simulation Kernel for System-level Models: A SystemC kernel for Synchronous Data Flow Models.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 8, pp. 1261–1271, 2005.
UMoC++: Modeling environment for heterogeneous systems based on generic MoCs.
In Advances in Design and Specification Languages for SoCs - Selected Contributions from FDL’05,
Springer Verlag, 2005
2004
Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models.
In proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 248–253, 2004.
Truly heterogeneous modeling with SystemC.
In Formal Models and Methods for System Design,
Edited by R. Gupta, P. Le Guernic, S. Shukla, and J. P. Talpin, Kluwer Academic Publishers Norwell, MA, USA, 2004, pp. pp. 88–101
Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models.
In proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Los Alamitos, CA, USA, pp. 241–242, 2004.
A survey of networked embedded systems: An introduction.
In Handbook of Information Technology,
CRC Press, 2004
A Functional Programming Framework for Heterogeneous Models of Computation for System Design.
In proceedings of Forum on Specification and Design Languages (FDL), pp. 586–598, 2004.
2003
Systematic abstractions of microprocessor RTL models to enhance simulation efficiency.
In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 103–108, 2003.