Publications

By Year By Type
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2022

2022

  • [1]
    Predictable Sharing of Last-level Cache Partitions for Multi-core Safety-critical Systems.
    By Wu, Z. and Patel, H.
    In proceedings of IEEE Design Automation Conference (DAC), pp. 1–6, 2022.
  • [2]
    Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs.
    By Prakash, S.K., Patel, H. and Kapre, N.
    In IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 1–9, 2022.
  • [3]
    Containerization and Orchestration of Software for Autonomous Mobile Robots: a Case Study of Mixed-Criticality Tasks across Edge-Cloud Computing Platforms.
    By Lumpp, F., Fummi, F., Patel, H. and Bombieri, N.
    In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pp. 1–7, 2022.
    •

    2021

  • [1]
    A Hardware Platform for Exploring Predictable Cache Coherence Protocols for Real-time Multicores .
    By Wu, Z., Kaushik, A.M. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, 2021.
  • [2]
    A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence.
    By Kaushik, A.M. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, 2021.
  • [3]
    Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols.
    By Kaushik, A.M. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1–6, 2021.
  • [4]
    A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms.
    By Lumpp, F., Patel, H. and Bombieri, N.
    In proceedings of IEEE Design Automation Conference (DAC), pp. 685–690, 2021.
  • [5]
    Task Mapping and Scheduling for OpenVX Applications on Heterogeneous Multi/Many-core Architectures.
    By Lumpp, F., Aldeheri, S., Patel, H. and Bombieri, N.
    In IEEE Transactions on Computers (TC), pp. 1–14, 2021.
  • [6]
    Automatic Construction of Predictable and High-Performance Cache Coherence Protocols for Multi-Core Real-Time Systems.
    By Kaushik, A.M. and Patel, H.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), p. 14, 2021.
    •

    2020

  • [1]
    Gretch: A Hardware Prefetcher for Graph Analytics.
    By Kaushik, A.M., Pekhimenko, G. and Patel, H.
    In ACM Transactions on Architecture and Code Optimization (TACO), pp. 1–25, Nov. 2020.
  • [2]
    Designing Predictable Cache Coherence for Multi-core Real-Time Systems.
    By Kaushik, A.M., Hassan, M. and Patel, H.
    In IEEE Transactions on Computers (TC), pp. 1–16, Nov. 2020.
  • [3]
    On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core Architectures.
    By Aldegheri, S., Bombieri, N. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1003–1006, 2020.
    •

    2019

  • [1]
    Technical Report: PENDULUM: A Cache Coherence Protocol for Mixed Criticality Systems.
    By Sritharan, N., Kaushik, A.M., Hassan, M. and Patel, H.
    Technical Report #CAESR-TR-2019-01, Dec-2019
  • [2]
    Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems.
    By Sritharan, N., Kaushik, A.M., Hassan, M. and Patel, H.
    In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, 2019.
  • [3]
    CARP: A Data Communication Mechanism for Multi-Core Mixed-Criticality Systems.
    By Kaushik, A.M., Tegegn, P., Wu, Z. and Patel, H.
    In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, 2019.
  • [4]
    Strengthening PUFs using Composition.
    By Wu, Z., Patel, H., Sachdev, M. and Tripunitara, M.
    In proceedings of IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–8, 2019.
  • [5]
    Strengthening PUFs using Composition.
    By Wu, Z., Patel, H., Sachdev, M. and Tripunitara, M.
    In IEEE Transactions on Computers, pp. 1–14, 2019.
  • [6]
    Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20, 2017].
    By Große, D., Vinco, S. and Patel, H. eds.
    Springer, 2019
    •

    2018

  • [1]
    A Comparative Study of Predictable DRAM Controllers.
    By Guo, D., Hassan, M., Pellizzoni, R. and Patel, H.
    In ACM Transactions on Embedded Computing Systems (TECS), vol. 17, pp. 53:1–53:23, Nov. 2018.
  • [2]
    Technical Report for Modeling Attacks on State-of-the-art PUF Architectures.
    By Wu, Z., Patel, H., Tripunitara, M. and Sachdev, M.
    Technical Report #CAESR-TR-2018-01, Jan-2018
  • [3]
    MCXplore: Automating the Validation Process of DRAM Memory Controller Designs.
    By Hassan, M. and Patel, H.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 5, pp. 1050–1063, 2018.
  • [4]
    Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis.
    By Hassan, M., Kaushik, A.M. and Patel, H.
    In ACM Transactions on Embedded Computing Systems (TECS), vol. 17, no. 5, pp. 90:1–90:25, 2018.
    •

    2017

  • [1]
    Technical Report for HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores.
    By Sritharan, N., Kaushik, A., Hassan, M. and Patel, H.
    Technical Report #CAESR-TR-2017-01, Dec-2017
  • [2]
    PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality.
    By Hassan, M., Patel, H. and Pellizzoni, R.
    In ACM Transactions on Embedded Computing Systems (TECS), vol. 16, pp. 100:1–100:28, May 2017.
  • [3]
    Predictable cache coherence for multi-core real time systems.
    By Hassan, M., Kaushik, A.M. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 235–246, 2017.
  • [4]
    HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems.
    By Sritharan, N., Kaushik, A.M., Hassan, M. and Patel, H.
    In CoRR, vol. abs/1706.07568, 2017.
  • [5]
    Applying Models of Computation to OpenCL Pipes for FPGA Computing.
    By Kapre, N. and Patel, H.
    In Proceedings of the 5th International Workshop on OpenCL, New York, NY, USA, pp. 9:1–9:4, 2017.
    •

    2016

  • [1]
    MCXplore: An Automated Framework for Validating Memory Controller Designs.
    By Hassan, M. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1357–1362, 2016.
  • [2]
    Path Selection for Real-Time Communication on Priority-Aware NoCs.
    By Kashif, H., Patel, H. and Fischmeister, S.
    In ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 53:1–53:25, Jul. 2016.
  • [3]
    Buffer Space Allocation for Real-Time Priority-Aware Networks.
    By Kashif, H. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 255–266, 2016.
  • [4]
    Criticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality Systems.
    By Hassan, M. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 73–83, 2016.
    •

    2015

  • [1]
    Reverse-engineering Embedded Memory Controllers through Latency-based analysis.
    By Hassan, M., Kaushik, A.M. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 297–306, 2015.
  • [2]
    A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems.
    By Hassan, M., Patel, H. and Pellizzoni, R.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 307–316, 2015.
  • [3]
    Static slack-based instrumentation of programs.
    By Kashif, H., Thomas, J.J., Patel, H. and Fischmeister, S.
    In 20th IEEE Conference on Emerging Technologies & Factory Automation, ETFA, pp. 1–8, 2015.
  • [4]
    SLA: A Stage-level Latency Analysis for Real-time Communication in a Pipelined Resource Model.
    By Kashif, H., Gholamian, S. and Patel, H.
    In IEEE Transactions on Computers, vol. 64, pp. 1177–1190, Apr. 2015.
    •

    2014

  • [1]
    Reliable Computing with Ultra-Reduced Instruction Set Co-processors.
    By Wang, D., Rajendiran, A., Ananthanarayanan, S., Patel, H., Tripunitara, M.V. and Garg, S.
    In IEEE Micro, vol. 34, no. 6, pp. 86–94, Dec. 2014.
  • [2]
    Bounding Buffer Space Requirements for Real-Time Priority-Aware Networks.
    By Kashif, H. and Patel, H.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 113–118, 2014.
  • [3]
    On the Semantics of Control-Operation-Integrated Synchronous Dataflow: Schedulability and Parallelism.
    By Bui, D., Lee, E.A. and Patel, H.
    In ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1–25, 2014.
    •

    2013

  • [1]
    An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
    By Prakash, A. and Patel, H.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 11, pp. 1819–1823, Nov. 2013.
  • [2]
    systemc-clang: An Open-source Framework for Analyzing Mixed-abstraction SystemC Models.
    By Kaushik, A.M. and Patel, H.
    In proceedings of IEEE Forum on Specification and Design Languages (FDL), pp. 1–8, 2013.
  • [3]
    ORTAP: An Offset-based Response Time Analysis for a Pipelined Communication Resource Model.
    By Kashif, H., Gholamian, S., Pellizzoni, R., Patel, H. and Fischmeister, S.
    In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 247–258, 2013.
  • [4]
    On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications.
    By Bertacco, V., Chatterjee, D., Bombieri, N., Fummi, F., Vinco, S., Kaushik, A.M. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1357–1366, 2013.
  • [5]
    Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors.
    By Ananthanarayanan, S., Garg, S. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 933–938, 2013.
    •

    2012

  • [1]
    Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors.
    By Ananthanarayanan, S., Garg, S. and Patel, H.
    In 3^rd Workshop on Resilient Architectures (WRA), In conjunction with IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 1–4, 2012.
  • [2]
    Accelerating SystemC Simulations using GPUs.
    By Nanjundappa, M., Kaushik, A.M., Patel, H. and Shukla, S.K.
    In proceedings of IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 132–139, 2012.
  • [3]
    synASM: A High-level Synthesis Framework that Supports Explicit Parallel and Timed Constructs.
    By Sinha, R. and Patel, H.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 10, pp. 1508–1521, Oct. 2012.
  • [4]
    Accelerating SystemC Simulations using GPUs.
    By Nanjundappa, M., Kaushik, A.M., Patel, H. and Shukla, S.K.
    Technical Report #CAESR-TR-2012-05, Sep-2012
  • [5]
    HolisticNoC: A NoC-Aware Holistic Analysis for Distributing Hard Real-time Systems on CMPs.
    By Gholamian, S., Kashif, H., Patel, H., Pellizzoni, R. and Fischmeister, S.
    Technical Report #CAESR-TR-2012-05, Sep-2012
  • [6]
    Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs.
    By Sinha, R., Prakash, A. and Patel, H.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 455–460, 2012.
  • [7]
    Predictable and Parallel Execution of Real-Time Applications on Cache-Coherent Multicores.
    By Pellizzoni, R., Betti, E. and Patel, H.
    In proceedings of IEEE Euromicro Conference on Real-Time Systems (ECRTS), pp. 1–10, 2012.
  • [8]
    Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs.
    By Kashif, H., Patel, H. and Fischmeister, S.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 499–504, 2012.
  • [9]
    A Link-level Analysis for Real-time Communication on Network-on-Chips.
    By Kashif, H., Gholamian, S., Patel, H. and Fischmeister, S.
    In proceedings of IEEE Euromicro Conference on Real-Time Systems (ECRTS), pp. 1–10, 2012.
  • [10]
    Reliable Computing with Ultra-Reduced Instruction-Set Co-processors.
    By Rajendiran, A., Ananthanarayanan, S., Patel, H., Tripunitara, M.V. and Garg, S.
    In proceedings of IEEE Design Automation Conference (DAC), New York, NY, USA, pp. 697–702, 2012.
  • [11]
    lintASM: Static Detection of State Conflicts for Explicitly Parallel and Timing Constructs in High-level Synthesis.
    By Sinha, R., Ravindran, K. and Patel, H.
    Technical Report #CAESR-TR-2012-05, Mar-2012
  • [12]
    Reliable Computing with Ultra-Reduced Instruction-Set Co-processors.
    By Rajendiran, A., Ananthanarayanan, S., Patel, H., Tripunitara, M.V. and Garg, S.
    Technical Report #CAESR-TR-2012-03, Mar-2012
  • [13]
    An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
    By Prakash, A. and Patel, H.
    Technical Report #CAESR-TR-2012-04, Mar-2012
  • [14]
    An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
    By Prakash, A. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 659–664, 2012.
  • [15]
    Robust Optimization for Power-Aware Capacity Planning of Heterogeneous Data Centers.
    By Garg, S., Sundaram, S. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1–6, 2012.
  • [16]
    Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs.
    By Sinha, R., Prakash, A. and Patel, H.
    Technical Report #CAESR-TR-2012-01, Jan-2012
  • [17]
    Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs.
    By Kashif, H., Patel, H. and Fischmeister, S.
    Technical Report #CAESR-TR-2012-02, Jan-2012
  • [18]
    Time-Aware Instrumentation on the Worst-Case Path.
    By Kashif, H., Thomas, J., Patel, H. and Fischmeister, S.
    In Real-Time Systems (RTS), pp. 1–12, 2012.
    •

    2011

  • [1]
    Robust Heterogeneous Data Center Design: A Principled Approach.
    By Garg, S., Sundaram, S. and Patel, H.
    In ACM SIGMETRICS Performance Evaluation Review (PER), vol. 39, no. 3, pp. 28–30, Dec. 2011.
  • [2]
    Time-aware Instrumentation of the Worst-case Path.
    By Kashif, H., Thomas, J., Patel, H. and Fischmeister, S.
    In proceedings of ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), pp. 1–10, 2011.
  • [3]
    A Link-level Analysis for Real-time Communication on Network-on-Chips.
    By Kashif, H., Gholamian, S., Patel, H. and Fischmeister, S.
    In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–10, 2011.
  • [4]
    PRET DRAM Controller: On the Virtue of Privitization.
    By Reineke, J., Liu, I., Patel, H., Kim, S. and Lee, E.A.
    In proceedings of ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES/ ISSS), pp. 99–108, 2011.
  • [5]
    An Authorization Scheme for Version Control Systems.
    By Chamarty, S., Patel, H. and Tripunitara, M.V.
    In proceedings of ACM Symposium on Access Control Models and Technologies (SACMAT), New York, NY, USA, pp. 123–132, 2011.
  • [6]
    Temporal Isolation on Multiprocessing Architectures.
    By Bui, D., Lee, E.A., Liu, I., Patel, H. and Reineke, J.
    In proceedings of IEEE Design Automation Conference (DAC), pp. 274–279, 2011.
  • [7]
    Abstract State Machines as an Intermediate Representation for High Level Synthesis.
    By Sinha, R. and Patel, H.
    In proceedings of IEEE Design, Automation and Test in Europe (DATE), pp. 1–6, 2011.
  • [8]
    A Case for Instruction Subset Architectures (I_SA) – Guaranteeing Functionality in High Defect Rate Technologies.
    By Patel, H. and Garg, S.
    In ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Session on Ideas and Perspectives, pp. 1–2, 2011.
  • [9]
    Extending Force-directed Scheduling with Explicit Parallel and Timed Constructs for High-level Synthesis.
    By Sinha, R. and Patel, H.
    In proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 214–217, 2011.
  • [10]
    Robust Heterogeneous Data Center Design:A Principled Approach.
    By Garg, S., Sundaram, S. and Patel, H.
    In proceedings of Workshop on Mathematical Performance Modeling and Analysis (MAMA), pp. 1–4, 2011.
  • [11]gitolite. https://github.com/sitaramc/gitolite, 2011
    •

    2010

  • [1]
    A Hardware/Software Co-design Framework using Abstract State Machines.
    By Buchanan, N. and Patel, H.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 53–58, 2010.
  • [2]
    Deploying Hard Real-time Control Software on CMPs.
    By Bui, D., Patel, H. and Lee, E.A.
    In International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 283–292, 2010.
  • [3]
    Towards A Multi-MoC Hardware/Software Co-design Framework using Abstract State Machines.
    By Buchanan, N. and Patel, H.
    Technical Report #CAESR-TR-2010-01, Jan-2010
  • [4]
    SCGPSim: A fast SystemC simulator on GPUs.
    By Nanjundappa, M., Patel, H., Jose, B.A. and Shukla, S.K.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 149–154, 2010.
    •

    2009

  • [1]
    A Disruptive Computer Design Idea: Architectures with Repeatable Timing.
    By Edwards, S.A., Kim, S., Lee, E.A., Liu, I., Patel, H. and Schoeberl, M.
    In proceedings of IEEE International Conference on Computer Design (ICCD), pp. 54–59, 2009.
  • [2]
    Generating Multi-threaded code from Polychronous Specifications.
    By Jose, B.A., Patel, H., Shukla, S.K. and Talpin, J.-P.
    In Electronic Notes in Theoretical Computer Science, vol. 238, no. 1, pp. 57–69, Jun. 2009.
  • [3]
    Poster Abstract: Timing Instructions - ISA Extensions for Timing Guarantees.
    By Liu, I., Lickly, B., Patel, H. and Lee, E.A.
    In proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–2, 2009.
  • [4]
    Using a Model Checker to Determine Worst-case Execution Time.
    By Kim, S., Patel, H. and Edwards, S.A.
    Computer Science Technical Report
    Technical Report #CUCS-038-09, 2009
  • [5]
    Reconciling repeatable timing with pipelining and memory hierarchy.
    By Edward, S.A., Kim, S., Lee, E.A., Patel, H. and Schoeberl, M.
    In proceedings of the Workshop on Reconciling Performance with Predictability (RePP), pp. 1–6, 2009.
    •

    2008

  • [1]
    A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture.
    By Patel, H., Lickly, B., Burgers, B. and Lee, E.A.
    EECS Department, University of California, Berkeley
    Technical Report #UCB/EECS-2008-115, Nov-2008
  • [2]
    Predictable Programming on a Precision Timed Architecture.
    By Lickly, B., Liu, I., Kim, S., Patel, H., Edwards, S.A. and Lee, E.A.
    In proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), pp. 137–146, 2008.
  • [3]
    An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture.
    By Forbes, S.-S., Andrade, H., Patel, H. and Lee, E.A.
    In proceedings of the IEEE International Symposium on Distributed Simulation and Real Time Applications (DSRT), pp. 322–325, 2008.
  • [4]
    A Scratchpad Memory Allocation Scheme for Dataflow Models.
    By Bandyopadhyay, S., Feng, T.H., Patel, H. and Lee, E.A.
    EECS Department, University of California, Berkeley
    Technical Report #UCB/EECS-2008-104, Aug-2008
  • [5]
    Ingredients for Successful System Level Design Methodology.
    By Patel, H. and Shukla, S.K.
    Springer Netherlands, pp. p. 208, , 2008
  • [6]
    SML-Sys: A Functional Framework with Multiple Models of Computation for Modeling Heterogeneous System.
    By Mathaikutty, D.A., Patel, H., Shukla, S.K. and Jantsch, A.
    In Design Automation for Embedded Systems, vol. 12, no. 1–2, pp. 1–30, Jun. 2008.
  • [7]
    On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications.
    By Jose, B.A., Shukla, S.K., Patel, H. and Talpin, J.-P.
    In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 129–138, 2008.
  • [8]
    EWD: A Metamodeling Driven Customizable Multi-MoC System Modeling Environment.
    By Mathaikutty, D.A., Patel, H., Shukla, S.K. and Jantsch, A.
    In ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 12, no. 3, pp. 1–43, May 2008.
  • [9]
    PTIDES: A Programming Model for Distributed Real-Time Embedded Systems.
    By Derler, P., Feng, T.H., Lee, E.A., Matic, S., Patel, H., Zhao, Y. and Zou, J.
    EECS Department, University of California, Berkeley
    Technical Report #UCB/EECS-2008-72, May-2008
  • [10]
    Model-driven Validation of SystemC Designs.
    By Patel, H. and Shukla, S.K.
    In EURASIP Journal on Embedded Systems, vol. 2008, pp. 1–14, Apr. 2008.
  • [11]
    Toward an Effective Execution Policy for Distributed Real-Time Embedded Systems.
    By Feng, T.H., Lee, E.A., Patel, H. and Zou, J.
    In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Work-in-Progress Session, pp. 1–4, 2008.
  • [12]
    Exploring Power Management in Multi-core Systems.
    By Bergamaschi, R.A., Han, G., Buyuktosunoglu, A., Patel, H., Nair, I., Dittmann, G., Janssen, G., Dhanwada, N., Hu, Z., Bose, P. and Darringer, J.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 708–713, 2008.
  • [13]
    On Cosimulating Multiple Abstraction-Level System-Level Models.
    By Patel, H. and Shukla, S.K.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 2, pp. 394–398, Feb. 2008.
    •

    2007

  • [1]
    Model-driven Validation of SystemC Designs.
    By Patel, H. and Shukla, S.K.
    In proceedings of ACM/IEEE Design Automation Conference (DAC), New York, NY, USA, pp. 29–34, 2007.
  • [2]
    Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL.
    By Patel, H. and Shukla, S.K.
    In proceedings of Design, Automation and Test in Europe Conference (DATE), pp. 279–284, 2007.
  • [3]
    Heterogeneous Behavioral Hierarchy Extensions for SystemC.
    By Patel, H., Shukla, S.K. and Bergamaschi, R.A.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 4, pp. 765–780, Apr. 2007.
  • [4]
    Performance modeling for early analysis of multi-core systems.
    By Bergamaschi, R.A., Nair, I., Dittmann, G., Patel, H., Janssen, G., Dhanwada, N., Buyuktosunoglu, A., Acar, E., Nam, G.-joon, Kucar, D., Bose, P., Darringer, J. and Han, G.
    In proceedings of IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis (CODES/ISSS), pp. 209–214, 2007.
    •

    2006

  • [1]
    Deep vs. Shallow, Kernel vs. Language–What is Better for Heterogeneous Modeling in SystemC?
    By Patel, H. and Shukla, S.K.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 68–75, 2006.
  • [2]
    CARH: A Service-oriented Architecture for Validating System-level Designs.
    By Patel, H., Mathaikutty, D.A., Berner, D. and Shukla, S.K.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 8, pp. 1458–1474, Aug. 2006.
  • [3]
    A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design.
    By Patel, H., Shukla, S.K., Mednick, E. and Nikhil, R.S.
    In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 39–48, 2006.
  • [4]
    Heterogeneous Behavioral Hierarchy for System Level Designs.
    By Patel, H., Shukla, S.K. and Bergamaschi, R.A.
    In proceedings of Design, Automation and Test in Europe (DATE), pp. 565–570, 2006.
  • [5]
    Design Issues for Networked Embedded Systems.
    By Patel, H., Gupta, S., Shukla, S.K. and Gupta, R.
    In Handbook of Information Technology,
    R. Zurawski, Ed.
    CRC Press, 2006, pp. pp. 1–18
    •

    2005

  • [1]
    Automated Extraction of Structural Information from SystemC-based IP for Validation.
    By Berner, D., Patel, H., Mathaikutty, D.A. and Shukla, S.K.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 99–104, 2005.
  • [2]
    Towards Behavioral Hierarchy Extensions for SystemC.
    By Patel, H. and Shukla, S.K.
    In proceedings of Forum on Design and Specification Languages (FDL), pp. 361–373, 2005.
  • [3]
    Modeling environment for heterogeneous systems based on generic MoCs.
    By Mathaikutty, D.A., Patel, H., Shukla, S.K. and Jantsch, A.
    In proceedings of Forum on Design and Specification Languages (FDL), pp. 291–303, 2005.
  • [4]
    SystemCXML: An extensible SystemC front end using XML.
    By Berner, D., Patel, H., Mathaikutty, D.A., Talpin, J.-P. and Shukla, S.K.
    In proceedings of Forum on Design and Specification Languages (FDL), pp. 405–409, 2005.
  • [5]
    SystemC Kernel Extensions for Heterogeneous System Modeling.
    By Patel, H. and Shukla, S.K.
    Springer United States, pp. p. 172, , 2005
  • [6]
    Towards a Heterogeneous Simulation Kernel for System-level Models: A SystemC kernel for Synchronous Data Flow Models.
    By Patel, H. and Shukla, S.K.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 8, pp. 1261–1271, 2005.
  • [7]
    UMoC++: Modeling environment for heterogeneous systems based on generic MoCs.
    By Mathaikutty, D.A., Patel, H., Shukla, S.K. and Jantsch, A.
    In Advances in Design and Specification Languages for SoCs - Selected Contributions from FDL’05,
    Springer Verlag, 2005
    •

    2004

  • [1]
    Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models.
    By Patel, H. and Shukla, S.K.
    In proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 248–253, 2004.
  • [2]
    Truly heterogeneous modeling with SystemC.
    By Patel, H. and Shukla, S.K.
    In Formal Models and Methods for System Design,
    Edited by R. Gupta, P. Le Guernic, S. Shukla, and J. P. Talpin, Kluwer Academic Publishers Norwell, MA, USA, 2004, pp. pp. 88–101
  • [3]
    Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models.
    By Patel, H. and Shukla, S.K.
    In proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Los Alamitos, CA, USA, pp. 241–242, 2004.
  • [4]
    A survey of networked embedded systems: An introduction.
    By Patel, H., Gupta, S., Shukla, S.K. and Gupta, R.
    In Handbook of Information Technology,
    CRC Press, 2004
  • [5]
    A Functional Programming Framework for Heterogeneous Models of Computation for System Design.
    By Mathaikutty, D.A., Patel, H. and Shukla, S.K.
    In proceedings of Forum on Specification and Design Languages (FDL), pp. 586–598, 2004.
    •

    2003

  • [1]
    Systematic abstractions of microprocessor RTL models to enhance simulation efficiency.
    By Bhaduri, D., Chandra, M., Patel, H., Sharad, S. and Suhaib, S.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 103–108, 2003.
    •