Publications

By Year By Type
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Journals

  1. TVLSI
    Enhancing Strong PUF Security With Nonmonotonic Response Quantization
    Stangherlin, Hugo, Wu, Zhuanhao, Patel, Hiren, and Sachdev, Manoj
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 55-64, Jan, 2023
  2. TCAD
    Automatic Construction of Predictable and High-Performance Cache Coherence Protocols for Multi-Core Real-Time Systems
    Kaushik, Anirudh M., and Patel, Hiren
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 14, Oct, 2022
    IEEE Code
  3. TCOMP
    Task Mapping and Scheduling for OpenVX Applications on Heterogeneous Multi/Many-core Architectures
    Lumpp, Francesco, Aldeheri, Stefano, Patel, Hiren, and Bombieri, Nicola
    IEEE Transactions on Computers (TCOMP), pp. 1–14, Oct, 2021
    IEEE
  4. TACO
    Gretch: A Hardware Prefetcher for Graph Analytics
    Kaushik, Anirudh M., Pekhimenko, Gennady, and Patel, Hiren
    ACM Transactions on Architecture and Code Optimization (TACO), pp. 1–25, Nov, 2020
    PDF
  5. TCOMP
    Designing Predictable Cache Coherence for Multi-core Real-Time Systems
    Kaushik, Anirudh M., Hassan, Mohamed, and Patel, Hiren
    IEEE Transactions on Computers (TCOMP), pp. 1–16, Nov, 2020
    Code
  6. TECS
    A Comparative Study of Predictable DRAM Controllers
    Guo, Danlu, Hassan, Mohamed, Pellizzoni, Rodolfo, and Patel, Hiren
    ACM Transactions on Embedded Computing Systems (TECS), pp. 53:1–53:23, Nov, 2018
  7. TECS
    Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis
    Hassan, Mohamed, Kaushik, Anirudh M., and Patel, Hiren
    ACM Transactions on Embedded Computing Systems (TECS), pp. 90:1–90:25, Nov, 2018
  8. TCAD
    MCXplore: Automating the Validation Process of DRAM Memory Controller Designs
    Hassan, Mohamed, and Patel, Hiren
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1050–1063, Nov, 2018
  9. TECS
    PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality
    Hassan, Mohamed, Patel, Hiren, and Pellizzoni, Rodolfo
    ACM Transactions on Embedded Computing Systems (TECS), pp. 100:1–100:28, May, 2017
  11. TODAES
    Path Selection for Real-Time Communication on Priority-Aware NoCs
    Kashif, Hany, Patel, Hiren, and Fischmeister, Sebastian
    ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 53:1–53:25, Jul, 2016
  12. TCOMP
    SLA: A Stage-level Latency Analysis for Real-time Communication in a Pipelined Resource Model
    Kashif, Hany, Gholamian, Sina, and Patel, Hiren
    IEEE Transactions on Computers (TCOMP), pp. 1177–1190, Apr, 2015
  13. DAC
    Reliable Computing with Ultra-Reduced Instruction Set Co-processors
    Wang, Dan, Rajendiran, Aravindkumar, Ananthanarayanan, Sundaram, Patel, Hiren, Tripunitara, Mahesh V., and Garg, Siddharth
    IEEE Micro, pp. 86–94, Dec, 2014
  15. TCAD
    An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture
    Prakash, Aayush, and Patel, Hiren
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1819–1823, Nov, 2013
  16. TCAD
    synASM: A High-level Synthesis Framework that Supports Explicit Parallel and Timed Constructs
    Sinha, Rohit, and Patel, Hiren
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1508–1521, Oct, 2012
  18. PER
    Robust Heterogeneous Data Center Design: A Principled Approach
    Garg, Siddharth, Sundaram, Shreyas, and Patel, Hiren
    ACM SIGMETRICS Performance Evaluation Review (PER), pp. 28–30, Dec, 2011
  19. ENTCS
    Generating Multi-threaded code from Polychronous Specifications
    Jose, Bijoy A., Patel, Hiren, Shukla, Sandeep K., and Talpin, Jean-Pierre
    Electronic Notes in Theoretical Computer Science, pp. 57–69, Jun, 2009
  20. DAES
    SML-Sys: A Functional Framework with Multiple Models of Computation for Modeling Heterogeneous System
    Mathaikutty, Deepak A., Patel, Hiren, Shukla, Sandeep K., and Jantsch, Axel
    Design Automation for Embedded Systems, pp. 1–30, Jun, 2008
  21. TODAES
    EWD: A Metamodeling Driven Customizable Multi-MoC System Modeling Environment
    Mathaikutty, Deepak A., Patel, Hiren, Shukla, Sandeep K., and Jantsch, Axel
    ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1–43, May, 2008
  22. EURASIP
    Model-driven Validation of SystemC Designs
    Patel, Hiren, and Shukla, Sandeep K.
    EURASIP Journal on Embedded Systems, pp. 1–14, Apr, 2008
  23. TCAD
    On Cosimulating Multiple Abstraction-Level System-Level Models
    Patel, Hiren, and Shukla, Sandeep K.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 394–398, Feb, 2008
  24. TCAD
    Heterogeneous Behavioral Hierarchy Extensions for SystemC
    Patel, Hiren, Shukla, Sandeep K., and Bergamaschi, Reinaldo A.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 765–780, Apr, 2007
  25. TCAD
    CARH: A Service-oriented Architecture for Validating System-level Designs
    Patel, Hiren, Mathaikutty, Deepak A., Berner, David, and Shukla, Sandeep K.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1458–1474, Aug, 2006
  26. TCAD
    Towards a Heterogeneous Simulation Kernel for System-level Models: A SystemC kernel for Synchronous Data Flow Models
    Patel, Hiren, and Shukla, Sandeep K.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1261–1271, Aug, 2005

Conferences

  1. DATE
    Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems
    Wu, Zhuanhao, Bekmyrza, Marat, Kapre, Nachiket, and Patel, Hiren
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1–-6, Apr, 2023
    Nominated for best paper award.
    PDF
  2. FPT
    ZHW: A Numerical CODEC for Big Data Scientific Computation
    Barrow, Michael, Wu, Zhuanhao, Lloyd, Scott, Gokhale, Maya, Patel, Hiren, and Lindstrom, Peter
    In International Conference on Field-Programmable Technology (FPT), pp. 1-9, Apr, 2022
    IEEE Code
  3. FCCM
    Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs
    Prakash, Srinirdheeshwar Kuttuva, Patel, Hiren, and Kapre, Nachiket
    In IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 1-9, Apr, 2022
    IEEE
  4. DAC
    Predictable Sharing of Last-level Cache Partitions for Multi-core Safety-critical Systems
    Wu, Zhuanhao, and Patel, Hiren
    In proceedings of IEEE Design Automation Conference (DAC), pp. 1273–1278, Apr, 2022
    PDF
  5. IROS
    Containerization and Orchestration of Software for Autonomous Mobile Robots: a Case Study of Mixed-Criticality Tasks across Edge-Cloud Computing Platforms
    Lumpp, Francesco, Fummi, Franco, Patel, Hiren, and Bombieri, Nicola
    In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pp. 1–7, Apr, 2022
  6. RTAS
    A Hardware Platform for Exploring Predictable Cache Coherence Protocols for Real-time Multicores
    Wu, Zhuanhao, Kaushik, Anirudh M., and Patel, Hiren
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, May, 2021
    IEEE PDF Code
  7. RTAS
    A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence
    Kaushik, Anirudh M., and Patel, Hiren
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, May, 2021
    IEEE
  8. DATE
    Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols
    Kaushik, Anirudh M., and Patel, Hiren
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1–6, Mar, 2021
    IEEE PDF Code
  9. DAC
    A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms
    Lumpp, Francesco, Patel, Hiren, and Bombieri, Nicola
    In proceedings of IEEE Design Automation Conference (DAC), pp. 685–690, Mar, 2021
    PDF
  10. DATE
    On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core Architectures
    Aldegheri, Stefano, Bombieri, Nicola, and Patel, Hiren
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1003–1006, Mar, 2020
  11. RTSS
    CARP: A Data Communication Mechanism for Multi-Core Mixed-Criticality Systems
    Kaushik, Anirudh M., Tegegn, Paulos, Wu, Zhuanhao, and Patel, Hiren
    In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, Dec, 2019
    PDF
  12. RTSS
    Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems
    Sritharan, Nivedita, Kaushik, Anirudh M., Hassan, Mohamed, and Patel, Hiren
    In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, Dec, 2019
  13. ICCAD
    Strengthening PUFs using Composition
    Wu, Zhuanhao, Patel, Hiren, Sachdev, Manoj, and Tripunitara, Mahesh
    In proceedings of IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–8, Nov, 2019
    PDF
  14. RTAS
    Predictable cache coherence for multi-core real time systems
    Hassan, Mohamed, Kaushik, Anirudh M., and Patel, Hiren
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 235–246, Apr, 2017
    PDF Code
  15. IWOCL
    Applying Models of Computation to OpenCL Pipes for FPGA Computing
    Kapre, Nachiket, and Patel, Hiren
    In Proceedings of the 5th International Workshop on OpenCL, pp. 9:1–9:4, Apr, 2017
  16. DATE
    MCXplore: An Automated Framework for Validating Memory Controller Designs
    Hassan, Mohamed, and Patel, Hiren
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1357–1362, Sep, 2016
    Code
  17. RTAS
    Buffer Space Allocation for Real-Time Priority-Aware Networks
    Kashif, Hany, and Patel, Hiren
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 255–266, Apr, 2016
  18. RTAS
    Criticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality Systems
    Hassan, Mohamed, and Patel, Hiren
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 73–83, Apr, 2016
  19. RTAS
    Reverse-engineering Embedded Memory Controllers through Latency-based analysis
    Hassan, Mohamed, Kaushik, Anirudh M., and Patel, Hiren
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 297–306, Dec, 2015
  20. RTAS
    A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems
    Hassan, Mohamed, Patel, Hiren, and Pellizzoni, Rodolfo
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 307–316, Oct, 2015
  21. ETFA
    Static slack-based instrumentation of programs
    Kashif, Hany, Thomas, Johnson J., Patel, Hiren, and Fischmeister, Sebastian
    In 20th IEEE Conference on Emerging Technologies & Factory Automation, ETFA, pp. 1–8, Sep, 2015
  22. ASP-DAC
    Bounding Buffer Space Requirements for Real-Time Priority-Aware Networks
    Kashif, Hany, and Patel, Hiren
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 113–118, Jul, 2014
    Best paper candidate.
  23. FDL
    systemc-clang: An Open-source Framework for Analyzing Mixed-abstraction SystemC Models
    Kaushik, Anirudh M., and Patel, Hiren
    In proceedings of IEEE Forum on Specification and Design Languages (FDL), pp. 1–8, Sep, 2013
  24. RTAS
    ORTAP: An Offset-based Response Time Analysis for a Pipelined Communication Resource Model
    Kashif, Hany, Gholamian, Sina, Pellizzoni, Rodolfo, Patel, Hiren, and Fischmeister, Sebastian
    In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 247–258, Apr, 2013
  25. DATE
    Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors
    Ananthanarayanan, Sundaram, Garg, Siddharth, and Patel, Hiren
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 933–938, Mar, 2013
  26. DATE
    On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications
    Bertacco, Valeria, Chatterjee, Debapriya, Bombieri, Nicola, Fummi, Franco, Vinco, Sara, Kaushik, Anirudh M., and Patel, Hiren
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1357–1366, Mar, 2013
  28. HLDVT
    Accelerating SystemC Simulations using GPUs
    Nanjundappa, Mahesh, Kaushik, Anirudh M., Patel, Hiren, and Shukla, Sandeep K.
    In proceedings of IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 132–139, Nov, 2012
  31. ASP-DAC
    Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs
    Kashif, Hany, Patel, Hiren, and Fischmeister, Sebastian
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 499–504, Jul, 2012
  32. ASP-DAC
    Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs
    Sinha, Rohit, Prakash, Aayush, and Patel, Hiren
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 455–460, Jul, 2012
  33. DAC
    Reliable Computing with Ultra-Reduced Instruction-Set Co-processors
    Rajendiran, Aravindkumar, Ananthanarayanan, Sundaram, Patel, Hiren, Tripunitara, Mahesh V., and Garg, Siddharth
    In proceedings of IEEE Design Automation Conference (DAC), pp. 697–702, Jun, 2012
    PDF
  35. DATE
    An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture
    Prakash, Aayush, and Patel, Hiren
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 659–664, Mar, 2012
  38. CODES
    PRET DRAM Controller: On the Virtue of Privitization
    Reineke, Jan, Liu, Isaac, Patel, Hiren, Kim, Sungjun, and Lee, Edward A.
    In proceedings of ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES/ ISSS), pp. 99–108, Oct, 2011
  39. DAC
    Temporal Isolation on Multiprocessing Architectures
    Bui, Dai, Lee, Edward A., Liu, Isaac, Patel, Hiren, and Reineke, Jan
    In proceedings of IEEE Design Automation Conference (DAC), pp. 274–279, Jun, 2011
  40. SACMAT
    An Authorization Scheme for Version Control Systems
    Chamarty, Sitaram, Patel, Hiren, and Tripunitara, Mahesh V.
    In proceedings of ACM Symposium on Access Control Models and Technologies (SACMAT), pp. 123–132, Jun, 2011
  41. ASPLOS-I&P
    A Case for Instruction Subset Architectures (I_SA) – Guaranteeing Functionality in High Defect Rate Technologies
    Patel, Hiren, and Garg, Siddharth
    In ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Session on Ideas and Perspectives, pp. 1–2, Mar, 2011
  42. FCCM
    Abstract State Machines as an Intermediate Representation for High Level Synthesis
    Sinha, Rohit, and Patel, Hiren
    In proceedings of IEEE Design, Automation and Test in Europe (DATE), pp. 1–6, Mar, 2011
  43. MAMA
    Robust Heterogeneous Data Center Design:A Principled Approach
    Garg, Siddharth, Sundaram, Shreyas, and Patel, Hiren
    In proceedings of Workshop on Mathematical Performance Modeling and Analysis (MAMA), pp. 1–4, Mar, 2011
  44. FCCM
    Extending Force-directed Scheduling with Explicit Parallel and Timed Constructs for High-level Synthesis
    Sinha, Rohit, and Patel, Hiren
    In proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 214–217, Mar, 2011
  45. MTV
    A Hardware/Software Co-design Framework using Abstract State Machines
    Buchanan, Nathan, and Patel, Hiren
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 53–58, Dec, 2010
  46. RTCSA
    Deploying Hard Real-time Control Software on CMPs
    Bui, Dai, Patel, Hiren, and Lee, Edward A.
    In International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 283–292, Aug, 2010
  47. ASP-DAC
    SCGPSim: A fast SystemC simulator on GPUs
    Nanjundappa, Mahesh, Patel, Hiren, Jose, Bijoy A., and Shukla, Sandeep K.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 149–154, Aug, 2010
    Best paper award.
  48. ICCD
    A Disruptive Computer Design Idea: Architectures with Repeatable Timing
    Edwards, Stephen A., Kim, Sungjun, Lee, Edward A., Liu, Isaac, Patel, Hiren, and Schoeberl, Martin
    In proceedings of IEEE International Conference on Computer Design (ICCD), pp. 54–59, Oct, 2009
  49. RTAS-POSTER
    Poster Abstract: Timing Instructions - ISA Extensions for Timing Guarantees
    Liu, Isaac, Lickly, Ben, Patel, Hiren, and Lee, Edward A.
    In proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–2, Apr, 2009
  50. REPP-INVITED
    Reconciling repeatable timing with pipelining and memory hierarchy
    Edward, Stephen A., Kim, Sungjun, Lee, Edward A., Patel, Hiren, and Schoeberl, Martin
    In proceedings of the Workshop on Reconciling Performance with Predictability (RePP), pp. 1–6, Apr, 2009
  51. CASES
    Predictable Programming on a Precision Timed Architecture
    Lickly, Ben, Liu, Isaac, Kim, Sungjun, Patel, Hiren, Edwards, Stephen A., and Lee, Edward A.
    In proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), pp. 137-146, Oct, 2008
  52. DSRT
    An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture
    Forbes, Shanna-Shaye, Andrade, Hugo, Patel, Hiren, and Lee, Edward A.
    In proceedings of the IEEE International Symposium on Distributed Simulation and Real Time Applications (DSRT), pp. 322–325, Oct, 2008
  53. MEMOCODE
    On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications
    Jose, Bijoy A., Shukla, Sandeep K., Patel, Hiren, and Talpin, Jean-Pierre
    In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 129–138, Jun, 2008
  54. RTAS-WIP
    Toward an Effective Execution Policy for Distributed Real-Time Embedded Systems
    Feng, Thomas Huining, Lee, Edward A., Patel, Hiren, and Zou, Jia
    In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Work-in-Progress Session, pp. 1–4, Apr, 2008
  55. ASP-DAC
    Exploring Power Management in Multi-core Systems
    Bergamaschi, Reinaldo A., Han, Guoling, Buyuktosunoglu, A., Patel, Hiren, Nair, I., Dittmann, G., Janssen, G., Dhanwada, N., Hu, Zhigang, Bose, P., and Darringer, J.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 708-713, Mar, 2008
  56. DAC
    Model-driven Validation of SystemC Designs
    Patel, Hiren, and Shukla, Sandeep K.
    In proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 29–34, Jun, 2007
  57. DATE
    Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL
    Patel, Hiren, and Shukla, Sandeep K.
    In proceedings of Design, Automation and Test in Europe Conference (DATE), pp. 279–284, May, 2007
  58. CODES
    Performance modeling for early analysis of multi-core systems
    Bergamaschi, Reinaldo A., Nair, Indira, Dittmann, Gero, Patel, Hiren, Janssen, Geert, Dhanwada, Nagu, Buyuktosunoglu, Alper, Acar, Emrah, Nam, Gi-joon, Kucar, Dorothy, Bose, Pradip, Darringer, John, and Han, Gualing
    In proceedings of IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis (CODES/ISSS), pp. 209–214, May, 2007
  59. Deep vs. Shallow, Kernel vs. Language–What is Better for Heterogeneous Modeling in SystemC?
    Patel, Hiren, and Shukla, Sandeep K.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 68–75, Dec, 2006
  60. MEMOCODE
    A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design
    Patel, Hiren, Shukla, Sandeep K., Mednick, Elliot, and Nikhil, Rishiyur S.
    In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 39–48, Jul, 2006
  61. DATE
    Heterogeneous Behavioral Hierarchy for System Level Designs
    Patel, Hiren, Shukla, Sandeep K., and Bergamaschi, Reinaldo A.
    In proceedings of Design, Automation and Test in Europe (DATE), pp. 565–570, Mar, 2006
  62. MTV
    Automated Extraction of Structural Information from SystemC-based IP for Validation
    Berner, David, Patel, Hiren, Mathaikutty, Deepak A., and Shukla, Sandeep K.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 99-104, Nov, 2005
  63. FDL
    SystemCXML: An extensible SystemC front end using XML
    Berner, David, Patel, Hiren, Mathaikutty, Deepak A., Talpin, Jean-Pierre, and Shukla, Sandeep K.
    In proceedings of Forum on Design and Specification Languages (FDL), pp. 405–409, Sep, 2005
  64. FDL
    Towards Behavioral Hierarchy Extensions for SystemC
    Patel, Hiren, and Shukla, Sandeep K.
    In proceedings of Forum on Design and Specification Languages (FDL), pp. 361–373, Sep, 2005
  65. FDL
    Modeling environment for heterogeneous systems based on generic MoCs
    Mathaikutty, Deepak A., Patel, Hiren, Shukla, Sandeep K., and Jantsch, Axel
    In proceedings of Forum on Design and Specification Languages (FDL), pp. 291–303, Sep, 2005
  66. GLSVLSI
    Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models
    Patel, Hiren, and Shukla, Sandeep K.
    In proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 248–253, Feb, 2004
  67. ISVLSI
    Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models
    Patel, Hiren, and Shukla, Sandeep K.
    In proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 241–242, Feb, 2004
  68. FDL
    A Functional Programming Framework for Heterogeneous Models of Computation for System Design
    Mathaikutty, Deepak A., Patel, Hiren, and Shukla, Sandeep K.
    In proceedings of Forum on Specification and Design Languages (FDL), pp. 586–598, Feb, 2004
  69. MTV
    Systematic abstractions of microprocessor RTL models to enhance simulation efficiency
    Bhaduri, Debayan, Chandra, Madhup, Patel, Hiren, Sharad, Shekhar, and Suhaib, Syed
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 103-108, May, 2003

Books

  1. Springer
    Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20, 2017]
    , 2019
  2. SPRINGER
    Ingredients for Successful System Level Design Methodology
    Patel, Hiren, and Shukla, Sandeep K.
    , pp. 208, Jun, 2008
  3. SPRINGER
    SystemC Kernel Extensions for Heterogeneous System Modeling
    Patel, Hiren, and Shukla, Sandeep K.
    , pp. 172, Jan, 2005

Book chapters

  1. CRC
    Design Issues for Networked Embedded Systems
    Patel, Hiren, Gupta, Sumit, Shukla, Sandeep K., and Gupta, Rajesh
    , pp. 1–18, 2006
  2. FDL
    UMoC++: Modeling environment for heterogeneous systems based on generic MoCs
    Mathaikutty, Deepak A., Patel, Hiren, Shukla, Sandeep K., and Jantsch, Axel
    , pp. 1–18, 2005
  3. CRC
    A survey of networked embedded systems: An introduction
    Patel, Hiren, Gupta, Sumit, Shukla, Sandeep K., and Gupta, Rajesh
    , pp. 1–18, 2004
  4. KLUWER
    Truly heterogeneous modeling with SystemC
    Patel, Hiren, and Shukla, Sandeep K.
    , pp. 88–101, 2004

Technical reports

  1. CAESR-TR-2019-01
    Technical Report: PENDULUM: A Cache Coherence Protocol for Mixed Criticality Systems
    Sritharan, Nivedita, Kaushik, Anirudh M., Hassan, Mohamed, and Patel, Hiren
    , pp. 1–11, Dec, 2019
  3. CAESR-TR-2017-01
    Technical Report for HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores
    Sritharan, Nividita, Kaushik, Anirudh, Hassan, Mohamed, and Patel, Hiren
    , pp. 1–8, Dec, 2017
  4. CAESR-TR-2012-05
    HolisticNoC: A NoC-Aware Holistic Analysis for Distributing Hard Real-time Systems on CMPs
    Gholamian, Sina, Kashif, Hany, Patel, Hiren, Pellizzoni, Rodolfo, and Fischmeister, Sebastian
    , pp. 1–7, Sep, 2012
  5. CAESR-TR-2012-05
    Accelerating SystemC Simulations using GPUs
    Nanjundappa, Mahesh, Kaushik, Anirudh M., Patel, Hiren, and Shukla, Sandeep K.
    , pp. 132–139, Sep, 2012
  6. CAESR-TR-2012-03
    Reliable Computing with Ultra-Reduced Instruction-Set Co-processors
    Rajendiran, Aravindkumar, Ananthanarayanan, Sundaram, Patel, Hiren, Tripunitara, Mahesh V., and Garg, Siddharth
    , pp. 1–6, Mar, 2012
  8. CAESR-TR-2012-04
    An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture
    Prakash, Aayush, and Patel, Hiren
    , pp. 1–6, Mar, 2012
  9. CAESR-TR-2012-02
    Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs
    Kashif, Hany, Patel, Hiren, and Fischmeister, Sebastian
    , pp. 1–6, Jan, 2012
  10. CAESR-TR-2012-01
    Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs
    Sinha, Rohit, Prakash, Aayush, and Patel, Hiren
    , pp. 1–6, Jan, 2012
  12. CUCS-038-09
    Using a Model Checker to Determine Worst-case Execution Time
    Kim, Sungjun, Patel, Hiren, and Edwards, Stephen A.
    , pp. 1–6, Jan, 2009
  13. UCB/EECS-2008-115
    A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture
    Patel, Hiren, Lickly, Ben, Burgers, Bas, and Lee, Edward A.
    , pp. 1–6, Nov, 2008
  14. UCB/EECS-2008-104
    A Scratchpad Memory Allocation Scheme for Dataflow Models
    Bandyopadhyay, Shamik, Feng, Thomas Huining, Patel, Hiren, and Lee, Edward A.
    , pp. 1–6, Aug, 2008
  15. UCB/EECS-2008-72
    PTIDES: A Programming Model for Distributed Real-Time Embedded Systems
    Derler, Patricia, Feng, Thomas Huining, Lee, Edward A., Matic, Slobodan, Patel, Hiren, Zhao, Yang, and Zou, Jia
    , pp. 1–6, May, 2008