Research Projects

Current

For current projects, please visit the main page.

Past

Stage-level Analysis (SLA): A Real-time Communication Analysis for Pipelined Communication Models

We develop a worst-case response time analysis for a pipelined communication resource model. This analysis incorporates pipelined and parallel transmission of data. It also accounts for computation and communication delays together to provide tight worst-case response time bounds. As an example, we have applied this analysis to real-time priority-aware network-on-chips. SLA provides the foundation on which we are developing path selection, mapping, and buffer-space allocation/assignment solutions for hard real-time embedded systems.

The Design and Analysis of DRAM Memory Controllers for Mixed-criticality Systems

We design DRAM memory controllers and its associated worst-case latency analyses to handle multiple criticality levels, and dynamic reconfiguration. The objective is to propose novel DRAM memory controllers, optimization frameworks, and analysis techniques to aggressively meet temporal and performance requirements of mixed-criticality systems.

URISC: Ultra-Reduced Instruction-set Co-processors

We present a low-cost fault recovery and detection technique called the URISC. URISC introduces a single-instruction set computer (implementing the SUBLEQ instruction) as a low-cost hardware co-processor. The SUBLEQ instruction is Turing-complete; thereby, allowing us to recode any instructions rendered faulty via a sequence of SUBLEQs. We also develop a compiler based on LLVM that translates faulty instructions into the sequence of SUBLEQs. A prototype on an FPGA with the TigerMIPS extended with URISC is developed. We also have a framework for performing fault injection experiments.

systemc-clang: Open-source Framework for Analyzing SystemC RTL and TLM Models

We present an open-source framework for analyzing SystemC models that consist of a mixture of register-transfer level, and transaction-level designs. We represent both structural and behavioural semantics of the models. For the behavioural semantics, we introduce a suspension-automaton. This representation can be used for multiple purposes such as static analysis of the model, code transformations, and optimizations. We use systemc-clang (built on clang to perform semantic-preserving translations to GPUs for accelerated performance. systemc-clang is available for download and use.

Scratchpad Memory Allocation for the Precision Timed Architecture

We propose a static instruction scratchpad memory allocation scheme for the precision timed architecture (PRET). Since PRET provides timing instructions to control the temporal execution of programs, the objective of the allocation scheme is to ensure that the explicitly specified temporal requirements are met. Furthermore, this allocation incorporates the timing requirements from multiple hardware threads of the PRET architecture. We formulate the allocation problem as an integer-linear programming problem, and we implement a tool that takes compiled ARMv4 binaries, constructs a timing-requirements aware control-flow graph, performs a WCET analysis and SPM allocation, and rewrites the binaries with the allocation.

gitolite: An Authorization Scheme for VCSes

We present gitolite, an authorization scheme for Version Control Systems (VCSes). We have implemented it for the Git VCS. Our main consideration behind the design of gitolite is the balance between expressive power, correctness and usability in realistic settings. We discuss our design of gitolite, and in particular the four user-classes in its delegation model, and the administrative actions a user at each class performs. We also focus on expressing gitolite precisely in formal logic to give it a precise semantics and establish correctness properties. gitolite has been adopted in open-source software development, university and industry settings. gitolite is available for download and use.

synASM: A High-level Synthesis Framework with Support for Parallel and Timed Constructs

This work presents a high-level synthesis framework called synASM that synthesizes Abstract State Machines (ASMs) to VHDL for FPGAs. In particular, we focus on the specification, scheduling, and synthesis of parallel and timed constructs. ASMs possess well-defined formal semantics for sequential, and parallel computation, and their composition. We extend ASMs to support the specification of timing requirements, which we call timed constructs. We also describe the composition of timed constructs with sequential and parallel computation. A key contribution of this work is the extension of the force-directed scheduling algorithm to support both parallel and timed constructs. We implement the synthesis back-end in synASM that targets FPGAs.