Research Focus

Our research is in the design and analysis of embedded systems including both software and hardware aspects. Of particular interest are topics such as real-time embedded systems, embedded software, and computer architecture.

Recent Publications

  1. [J15]
    PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality.
    By Hassan, M., Patel, H. and Pellizzoni, R.
    In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–25, 2017.
  2. [J14]
    Path Selection for Real-Time Communication on Priority-Aware NoCs.
    By Kashif, H., Patel, H. and Fischmeister, S.
    In ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1–25, Jan. 2016.
  3. [C49]
    Predictable cache coherence for multi-core real time systems.
    By Hassan, M., Kaushik, A. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, 2017.

Current Projects

Predictable Access to Shared Data for Multi-core Real-time Systems

We investigate hardware and software techniques to ensure predictable accesses to shared data. We expect deployments of modern mixed-criticality systems to compute on shared data, which must be accessed in a predictable way.

Computer Architecture Support for Complex Networks

We are investigating a combination of microarchitecture and compiler techniques to accelerate the performance of accessing complex networks on modern computing systems.

Past Projects

Stage-level Analysis (SLA): A Real-time Communication Analysis for Pipelined Communication Models

We develop a worst-case response time analysis for a pipelined communication resource model. This analysis incorporates pipelined and parallel transmission of data. It also accounts for computation and communication delays together to provide tight worst-case response time bounds. As an example, we have applied this analysis to real-time priority-aware network-on-chips. SLA provides the foundation on which we are developing path selection, mapping, and buffer-space allocation/assignment solutions for hard real-time embedded systems.

The Design and Analysis of DRAM Memory Controllers for Mixed-criticality Systems

We design DRAM memory controllers and its associated worst-case latency analyses to handle multiple criticality levels, and dynamic reconfiguration. The objective is to propose novel DRAM memory controllers, optimization frameworks, and analysis techniques to aggressively meet temporal and performance requirements of mixed-criticality systems.

URISC: Ultra-Reduced Instruction-set Co-processors

We present a low-cost fault recovery and detection technique called the URISC. URISC introduces a single-instruction set computer (implementing the SUBLEQ instruction) as a low-cost hardware co-processor. The SUBLEQ instruction is Turing-complete; thereby, allowing us to recode any instructions rendered faulty via a sequence of SUBLEQs. We also develop a compiler based on LLVM that translates faulty instructions into the sequence of SUBLEQs. A prototype on an FPGA with the TigerMIPS extended with URISC is developed. We also have a framework for performing fault injection experiments.

systemc-clang: Open-source Framework for Analyzing SystemC RTL and TLM Models

We present an open-source framework for analyzing SystemC models that consist of a mixture of register-transfer level, and transaction-level designs. We represent both structural and behavioural semantics of the models. For the behavioural semantics, we introduce a suspension-automaton. This representation can be used for multiple purposes such as static analysis of the model, code transformations, and optimizations. We use systemc-clang (built on clang to perform semantic-preserving translations to GPUs for accelerated performance. systemc-clang is available for download and use.

Selected Service

Prospective Students

Students must have a strong background in programming (both software and hardware). If you are applying to either the Computer Science or Electrical and Computer Engineering department, and are interested in this research, then please send me your CV. Unfortunately, it may not be possible to respond to all email.

Current Students

I am fortunate to have worked with the following outstanding students.

Ph.D. MASc
  • Nivedita Sritharan
  • Paulos Tegegn



  1. Mohamed Hassan, Winter 2016
  2. Hany Kashif, Fall 2015 (SOTI Research)


  1. Yunling Cui, Winter 2017 (Intel, Canada)
  2. Nathan Buchanan, Fall 2016 (Texas Instruments, USA)
  3. Zhuoran Yin, Winter 2015 (National Instruments)
  4. Anirudh Kaushik, Winter 2014 (IBM Toronto => PhD @ Waterloo)
  5. Aayush Prakash, Spring 2012 (IBM Toronto => Nvidia Canada)
  6. Sina Gholamian, Spring 2012 (Thalmic Labs.=>Qualcomm Canada=> PhD @ Waterloo)

Research Associates

  1. Dan Wang, Fall 2013 (Istuary)


  1. Hong Lu, Winter 2015
  2. Shaishav Siddhipuria, Winter 2015
  3. Abhimanyu Nath, Winter 2015
  4. Shabir Adeel, Spring 2014
  5. Kenan Ali (Sandvine), Spring 2012
  6. Ayush Gupta (Altera), Spring 2012
  7. Kang Yang (Apple), Winter 2012.
  8. Aravindkumar Rajendiran (LinkedIn), Spring 2011.
  9. Rohit Sinha, Summer 2011. (Continuing PhD at University of California, Berkeley)
  10. Zayan Hafeez, Winter 2011. (Broadcom)
  11. Yatin Manerkar, Winter 2011. (Continuing PhD at Princeton University)
  12. Talha Jawaid, Winter 2011. (Continuing MASc at University of Waterloo)
  13. Olga Nam, Winter 2011.


For undergraduate academic advising matters for Computer Engineers, please use

Department of Electrical and Computer Engineering,
University of Waterloo,
200 University Ave W, Waterloo, ON N2L 3G1, Canada.

Office: E5 4018
Tel: +1 519 888 4567
Fax: +1 519 746 7260