Predictable Access to Shared Data for Multi-core Real-time Systems
We investigate hardware and software techniques to ensure predictable accesses to shared data. We expect deployments of modern mixed-criticality systems to compute on shared data, which must be accessed in a predictable way.
Computer Architecture Support for Complex Networks
We are investigating a combination of microarchitecture and compiler techniques to accelerate the performance of accessing complex networks on modern computing systems.
Stage-level Analysis (SLA):
A Real-time Communication Analysis for Pipelined Communication Models
We develop a worst-case response time analysis for a pipelined communication resource model. This analysis incorporates pipelined and parallel transmission of data. It also accounts for computation and communication delays together to provide tight worst-case response time bounds. As an example, we have applied this analysis to real-time priority-aware network-on-chips. SLA provides the foundation on which we are developing path selection, mapping, and buffer-space allocation/assignment solutions for hard real-time embedded systems.
The Design and Analysis of DRAM Memory Controllers for Mixed-criticality Systems
We design DRAM memory controllers and its associated worst-case latency analyses to handle multiple criticality levels, and dynamic reconfiguration.
The objective is to propose novel DRAM memory controllers, optimization frameworks, and analysis techniques to aggressively meet temporal and performance requirements of mixed-criticality systems.
Ultra-Reduced Instruction-set Co-processors
We present a low-cost fault recovery and detection technique called the URISC.
URISC introduces a single-instruction set computer (implementing the SUBLEQ instruction) as a low-cost hardware co-processor. The SUBLEQ instruction is Turing-complete; thereby, allowing us to recode any instructions rendered faulty via a sequence of SUBLEQs.
We also develop a compiler based on LLVM
that translates faulty instructions into the sequence of SUBLEQs.
A prototype on an FPGA with the TigerMIPS extended with URISC is developed.
We also have a framework for performing fault injection experiments
Open-source Framework for Analyzing SystemC RTL and TLM Models
We present an open-source framework for analyzing SystemC models that consist of a mixture of register-transfer level, and transaction-level designs. We represent both structural and behavioural semantics of the models. For the behavioural semantics, we introduce a suspension-automaton. This representation can be used for multiple purposes such as static analysis of the model, code transformations, and optimizations. We use systemc-clang (built on clang
to perform semantic-preserving translations to GPUs for accelerated performance.
is available for download and use.