Paper accepted at RTAS 2023

Paper accepted at IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) 2023

  • Zhuanhao Wu and Anirudh Kaushik present an approach to design a last-level cache (LLC) architecture that does not increase the worst-case latency due to back-invalidations. Their work leverages an existing work called zero-invalidation-victim (ZIV) to eliminate back-invalidations, and proposes a policy on top of it that guarantees a bounded worst-case latency.