Projects

Current research projects. Earlier projects are described on the Research page.

Predictable Cache Coherence Hardware cache coherence for real-time and mixed-criticality multicores, with analyzable worst-case latency.

Predictable GPUs for Safety-critical Systems GPU micro-architecture and compiler support that make worst-case execution time analyzable.

Predictable Shared Last-level Caches Shared last-level caches for safety-critical multicores that add capacity without inflating worst-case latency.

RISC-V RVV · ARM SVE

Vector Extensions for High-performance Computing How well compilers and HPC applications use scalable vector extensions such as RISC-V RVV and ARM SVE.