Publications

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2017

  • [J15]
    PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality.
    By Hassan, M., Patel, H. and Pellizzoni, R.
    In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–25, 2017.
  • [C49]
    Predictable cache coherence for multi-core real time systems.
    By Hassan, M., Kaushik, A. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, 2017.
  • 2016

  • [J14]
    Path Selection for Real-Time Communication on Priority-Aware NoCs.
    By Kashif, H., Patel, H. and Fischmeister, S.
    In ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 53:1–53:25, Jul. 2016.
  • [C48]
    Buffer Space Allocation for Real-Time Priority-Aware Networks.
    By Kashif, H. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, 2016.
  • [C47]
    Criticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality Systems.
    By Hassan, M. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–11, 2016.
  • [C46]
    MCXplore: An Automated Framework for Validating Memory Controller Designs.
    By Hassan, M. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1–6, 2016.
  • 2015

  • [J13]
    SLA: A Stage-level Latency Analysis for Real-time Communication in a Pipelined Resource Model.
    By Kashif, H., Gholamian, S. and Patel, H.
    In IEEE Transactions on Computers, vol. 64, pp. 1177–1190, Apr. 2015.
  • [C45]
    Static slack-based instrumentation of programs.
    By Kashif, H., Thomas, J.J., Patel, H. and Fischmeister, S.
    In 20th IEEE Conference on Emerging Technologies & Factory Automation, ETFA, pp. 1–8, 2015.
  • [C44]
    Reverse-engineering Embedded Memory Controllers through Latency-based analysis.
    By Hassan, M., Kaushik, A.M. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 297–306, 2015.
  • [C43]
    A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems.
    By Hassan, M., Patel, H. and Pellizzoni, R.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 307–316, 2015.
  • 2014

  • [J12]
    Reliable Computing with Ultra-Reduced Instruction Set Co-processors.
    By Wang, D., Rajendiran, A., Ananthanarayanan, S., Patel, H., Tripunitara, M.V. and Garg, S.
    In IEEE Micro, vol. 34, no. 6, pp. 86–94, Dec. 2014.
  • [C42]
    Bounding Buffer Space Requirements for Real-Time Priority-Aware Networks.
    By Kashif, H. and Patel, H.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 113–118, 2014.
    Best paper candidate.
  • 2013

  • [J11]
    An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
    By Prakash, A. and Patel, H.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 11, pp. 1819–1823, Nov. 2013.
  • [C41]
    systemc-clang: An Open-source Framework for Analyzing Mixed-abstraction SystemC Models.
    By Kaushik, A.M. and Patel, H.
    In proceedings of IEEE Forum on Specification and Design Languages (FDL), pp. 1–8, 2013.
  • [C40]
    ORTAP: An Offset-based Response Time Analysis for a Pipelined Communication Resource Model.
    By Kashif, H., Gholamian, S., Pellizzoni, R., Patel, H. and Fischmeister, S.
    In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 247–258, 2013.
  • [C39]
    Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors.
    By Ananthanarayanan, S., Garg, S. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 933–938, 2013.
  • [C38]
    On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications.
    By Bertacco, V., Chatterjee, D., Bombieri, N., Fummi, F., Vinco, S., Kaushik, A.M. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 1357–1366, 2013.
  • 2012

  • [J10]
    synASM: A High-level Synthesis Framework that Supports Explicit Parallel and Timed Constructs.
    By Sinha, R. and Patel, H.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 10, pp. 1508–1521, Oct. 2012.
  • [C37]
    Reliable Computing with Ultra-Reduced Instruction-Set Co-processors.
    By Rajendiran, A., Ananthanarayanan, S., Patel, H., Tripunitara, M.V. and Garg, S.
    In proceedings of IEEE Design Automation Conference (DAC), New York, NY, USA, pp. 697–702, 2012.
  • [C36]
    Accelerating SystemC Simulations using GPUs.
    By Nanjundappa, M., Kaushik, A.M., Patel, H. and Shukla, S.K.
    In proceedings of IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 132–139, 2012.
  • [C35]
    An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
    By Prakash, A. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE), pp. 659–664, 2012.
  • [C34]
    Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs.
    By Kashif, H., Patel, H. and Fischmeister, S.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 499–504, 2012.
  • [C33]
    Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs.
    By Sinha, R., Prakash, A. and Patel, H.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 455–460, 2012.
  • [TR11]
    HolisticNoC: A NoC-Aware Holistic Analysis for Distributing Hard Real-time Systems on CMPs.
    By Gholamian, S., Kashif, H., Patel, H., Pellizzoni, R. and Fischmeister, S.
    Technical Report #CAESR-TR-2012-05, Sep-2012
  • [TR10]
    Reliable Computing with Ultra-Reduced Instruction-Set Co-processors.
    By Rajendiran, A., Ananthanarayanan, S., Patel, H., Tripunitara, M.V. and Garg, S.
    Technical Report #CAESR-TR-2012-03, Mar-2012
  • [TR9]
    Accelerating SystemC Simulations using GPUs.
    By Nanjundappa, M., Kaushik, A.M., Patel, H. and Shukla, S.K.
    Technical Report #CAESR-TR-2012-05, Sep-2012
  • [TR8]
    An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
    By Prakash, A. and Patel, H.
    Technical Report #CAESR-TR-2012-04, Mar-2012
  • [TR7]
    Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs.
    By Kashif, H., Patel, H. and Fischmeister, S.
    Technical Report #CAESR-TR-2012-02, Jan-2012
  • [TR6]
    Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs.
    By Sinha, R., Prakash, A. and Patel, H.
    Technical Report #CAESR-TR-2012-01, Jan-2012
  • 2011

  • [J9]
    Robust Heterogeneous Data Center Design: A Principled Approach.
    By Garg, S., Sundaram, S. and Patel, H.
    In ACM SIGMETRICS Performance Evaluation Review (PER), vol. 39, no. 3, pp. 28–30, Dec. 2011.
  • [C32]
    A Case for Instruction Subset Architectures (I_SA) – Guaranteeing Functionality in High Defect Rate Technologies.
    By Patel, H. and Garg, S.
    In ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Session on Ideas and Perspectives, pp. 1–2, 2011.
  • [C31]
    Temporal Isolation on Multiprocessing Architectures.
    By Bui, D., Lee, E.A., Liu, I., Patel, H. and Reineke, J.
    In proceedings of IEEE Design Automation Conference (DAC), pp. 274–279, 2011.
  • [C30]
    PRET DRAM Controller: On the Virtue of Privitization.
    By Reineke, J., Liu, I., Patel, H., Kim, S. and Lee, E.A.
    In proceedings of ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES/ ISSS), pp. 99–108, 2011.
  • [C29]
    Robust Heterogeneous Data Center Design:A Principled Approach.
    By Garg, S., Sundaram, S. and Patel, H.
    In proceedings of Workshop on Mathematical Performance Modeling and Analysis (MAMA), pp. 1–4, 2011.
  • [C28]
    An Authorization Scheme for Version Control Systems.
    By Chamarty, S., Patel, H. and Tripunitara, M.V.
    In proceedings of ACM Symposium on Access Control Models and Technologies (SACMAT), New York, NY, USA, pp. 123–132, 2011.
  • [C27]
    Extending Force-directed Scheduling with Explicit Parallel and Timed Constructs for High-level Synthesis.
    By Sinha, R. and Patel, H.
    In proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 214–217, 2011.
  • [C26]
    Abstract State Machines as an Intermediate Representation for High Level Synthesis.
    By Sinha, R. and Patel, H.
    In proceedings of IEEE Design, Automation and Test in Europe (DATE), pp. 1–6, 2011.
  • 2010

  • [C25]
    A Hardware/Software Co-design Framework using Abstract State Machines.
    By Buchanan, N. and Patel, H.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 53–58, 2010.
  • [C24]
    Deploying Hard Real-time Control Software on CMPs.
    By Bui, D., Patel, H. and Lee, E.A.
    In International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 283–292, 2010.
  • [C23]
    SCGPSim: A fast SystemC simulator on GPUs.
    By Nanjundappa, M., Patel, H., Jose, B.A. and Shukla, S.K.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 149–154, 2010.
    Best paper award.
  • [TR5]
    Towards A Multi-MoC Hardware/Software Co-design Framework using Abstract State Machines.
    By Buchanan, N. and Patel, H.
    Technical Report #CAESR-TR-2010-01, Jan-2010
  • 2009

  • [J8]
    Generating Multi-threaded code from Polychronous Specifications.
    By Jose, B.A., Patel, H., Shukla, S.K. and Talpin, J.-P.
    In Electronic Notes in Theoretical Computer Science, vol. 238, no. 1, pp. 57–69, Jun. 2009.
  • [C22]
    A Disruptive Computer Design Idea: Architectures with Repeatable Timing.
    By Edwards, S.A., Kim, S., Lee, E.A., Liu, I., Patel, H. and Schoeberl, M.
    In proceedings of IEEE International Conference on Computer Design (ICCD), pp. 54–59, 2009.
  • [C21]
    Reconciling repeatable timing with pipelining and memory hierarchy.
    By Edward, S.A., Kim, S., Lee, E.A., Patel, H. and Schoeberl, M.
    In proceedings of the Workshop on Reconciling Performance with Predictability (RePP), pp. 1–6, 2009.
  • [C20]
    Poster Abstract: Timing Instructions - ISA Extensions for Timing Guarantees.
    By Liu, I., Lickly, B., Patel, H. and Lee, E.A.
    In proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–2, 2009.
  • [TR4]
    Using a Model Checker to Determine Worst-case Execution Time.
    By Kim, S., Patel, H. and Edwards, S.A.
    Computer Science Technical Report
    Technical Report #CUCS-038-09, 2009
  • 2008

  • [J7]
    On Cosimulating Multiple Abstraction-Level System-Level Models.
    By Patel, H. and Shukla, S.K.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 2, pp. 394–398, Feb. 2008.
  • [J6]
    Model-driven Validation of SystemC Designs.
    By Patel, H. and Shukla, S.K.
    In EURASIP Journal on Embedded Systems, vol. 2008, pp. 1–14, Apr. 2008.
  • [J5]
    EWD: A Metamodeling Driven Customizable Multi-MoC System Modeling Environment.
    By Mathaikutty, D.A., Patel, H., Shukla, S.K. and Jantsch, A.
    In ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 12, no. 3, pp. 1–43, May 2008.
  • [J4]
    SML-Sys: A Functional Framework with Multiple Models of Computation for Modeling Heterogeneous System.
    By Mathaikutty, D.A., Patel, H., Shukla, S.K. and Jantsch, A.
    In Design Automation for Embedded Systems, vol. 12, no. 1–2, pp. 1–30, Jun. 2008.
  • [B2]
    Ingredients for Successful System Level Design Methodology.
    By Patel, H. and Shukla, S.K.
    Springer Netherlands, pp. p. 208, , 2008
  • [C19]
    Toward an Effective Execution Policy for Distributed Real-Time Embedded Systems.
    By Feng, T.H., Lee, E.A., Patel, H. and Zou, J.
    In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Work-in-Progress Session, pp. 1–4, 2008.
  • [C18]
    Exploring Power Management in Multi-core Systems.
    By Bergamaschi, R.A., Han, G., Buyuktosunoglu, A., Patel, H., Nair, I., Dittmann, G., Janssen, G., Dhanwada, N., Hu, Z., Bose, P. and Darringer, J.
    In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 708–713, 2008.
  • [C17]
    On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications.
    By Jose, B.A., Shukla, S.K., Patel, H. and Talpin, J.-P.
    In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 129–138, 2008.
  • [C16]
    Predictable Programming on a Precision Timed Architecture.
    By Lickly, B., Liu, I., Kim, S., Patel, H., Edwards, S.A. and Lee, E.A.
    In proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), pp. 137–146, 2008.
  • [C15]
    An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture.
    By Forbes, S.-S., Andrade, H., Patel, H. and Lee, E.A.
    In proceedings of the IEEE International Symposium on Distributed Simulation and Real Time Applications (DSRT), pp. 322–325, 2008.
  • [TR3]
    A Scratchpad Memory Allocation Scheme for Dataflow Models.
    By Bandyopadhyay, S., Feng, T.H., Patel, H. and Lee, E.A.
    EECS Department, University of California, Berkeley
    Technical Report #UCB/EECS-2008-104, Aug-2008
  • [TR2]
    PTIDES: A Programming Model for Distributed Real-Time Embedded Systems.
    By Derler, P., Feng, T.H., Lee, E.A., Matic, S., Patel, H., Zhao, Y. and Zou, J.
    EECS Department, University of California, Berkeley
    Technical Report #UCB/EECS-2008-72, May-2008
  • [TR1]
    A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture.
    By Patel, H., Lickly, B., Burgers, B. and Lee, E.A.
    EECS Department, University of California, Berkeley
    Technical Report #UCB/EECS-2008-115, Nov-2008
  • 2007

  • [J3]
    Heterogeneous Behavioral Hierarchy Extensions for SystemC.
    By Patel, H., Shukla, S.K. and Bergamaschi, R.A.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 4, pp. 765–780, Apr. 2007.
  • [C14]
    Performance modeling for early analysis of multi-core systems.
    By Bergamaschi, R.A., Nair, I., Dittmann, G., Patel, H., Janssen, G., Dhanwada, N., Buyuktosunoglu, A., Acar, E., Nam, G.-joon, Kucar, D., Bose, P., Darringer, J. and Han, G.
    In proceedings of IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis (CODES/ISSS), pp. 209–214, 2007.
  • [C13]
    Model-driven Validation of SystemC Designs.
    By Patel, H. and Shukla, S.K.
    In proceedings of ACM/IEEE Design Automation Conference (DAC), New York, NY, USA, pp. 29–34, 2007.
  • [C12]
    Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL.
    By Patel, H. and Shukla, S.K.
    In proceedings of Design, Automation and Test in Europe Conference (DATE), pp. 279–284, 2007.
  • 2006

  • [J2]
    CARH: A Service-oriented Architecture for Validating System-level Designs.
    By Patel, H., Mathaikutty, D.A., Berner, D. and Shukla, S.K.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 8, pp. 1458–1474, Aug. 2006.
  • [BC4]
    Design Issues for Networked Embedded Systems.
    By Patel, H., Gupta, S., Shukla, S.K. and Gupta, R.
    In Handbook of Information Technology,
    R. Zurawski, Ed.
    CRC Press, 2006, pp. pp. 1–18
  • [C11]
    Deep vs. Shallow, Kernel vs. Language–What is Better for Heterogeneous Modeling in SystemC?
    By Patel, H. and Shukla, S.K.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 68–75, 2006.
  • [C10]
    Heterogeneous Behavioral Hierarchy for System Level Designs.
    By Patel, H., Shukla, S.K. and Bergamaschi, R.A.
    In proceedings of Design, Automation and Test in Europe (DATE), pp. 565–570, 2006.
  • [C9]
    A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design.
    By Patel, H., Shukla, S.K., Mednick, E. and Nikhil, R.S.
    In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 39–48, 2006.
  • 2005

  • [J1]
    Towards a Heterogeneous Simulation Kernel for System-level Models: A SystemC kernel for Synchronous Data Flow Models.
    By Patel, H. and Shukla, S.K.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 8, pp. 1261–1271, 2005.
  • [B1]
    SystemC Kernel Extensions for Heterogeneous System Modeling.
    By Patel, H. and Shukla, S.K.
    Springer United States, pp. p. 172, , 2005
  • [BC3]
    UMoC++: Modeling environment for heterogeneous systems based on generic MoCs.
    By Mathaikutty, D.A., Patel, H., Shukla, S.K. and Jantsch, A.
    In Advances in Design and Specification Languages for SoCs - Selected Contributions from FDL’05,
    Springer Verlag, 2005
  • [C8]
    Automated Extraction of Structural Information from SystemC-based IP for Validation.
    By Berner, D., Patel, H., Mathaikutty, D.A. and Shukla, S.K.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 99–104, 2005.
  • [C7]
    SystemCXML: An extensible SystemC front end using XML.
    By Berner, D., Patel, H., Mathaikutty, D.A., Talpin, J.-P. and Shukla, S.K.
    In proceedings of Forum on Design and Specification Languages (FDL), pp. 405–409, 2005.
  • [C6]
    Towards Behavioral Hierarchy Extensions for SystemC.
    By Patel, H. and Shukla, S.K.
    In proceedings of Forum on Design and Specification Languages (FDL), pp. 361–373, 2005.
  • [C5]
    Modeling environment for heterogeneous systems based on generic MoCs.
    By Mathaikutty, D.A., Patel, H., Shukla, S.K. and Jantsch, A.
    In proceedings of Forum on Design and Specification Languages (FDL), pp. 291–303, 2005.
  • 2004

  • [BC2]
    A survey of networked embedded systems: An introduction.
    By Patel, H., Gupta, S., Shukla, S.K. and Gupta, R.
    In Handbook of Information Technology,
    CRC Press, 2004
  • [BC1]
    Truly heterogeneous modeling with SystemC.
    By Patel, H. and Shukla, S.K.
    In Formal Models and Methods for System Design,
    Edited by R. Gupta, P. Le Guernic, S. Shukla, and J. P. Talpin, Kluwer Academic Publishers Norwell, MA, USA, 2004, pp. pp. 88–101
  • [C4]
    Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models.
    By Patel, H. and Shukla, S.K.
    In proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 248–253, 2004.
  • [C3]
    Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models.
    By Patel, H. and Shukla, S.K.
    In proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Los Alamitos, CA, USA, pp. 241–242, 2004.
  • [C2]
    A Functional Programming Framework for Heterogeneous Models of Computation for System Design.
    By Mathaikutty, D.A., Patel, H. and Shukla, S.K.
    In proceedings of Forum on Specification and Design Languages (FDL), pp. 586–598, 2004.
  • 2003

  • [C1]
    Systematic abstractions of microprocessor RTL models to enhance simulation efficiency.
    By Bhaduri, D., Chandra, M., Patel, H., Sharad, S. and Suhaib, S.
    In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 103–108, 2003.